Phuong Cao is a scientist at the National Center for Supercomputing Applications (NCSA) at the University of Illinois at Urbana-Champaign. His research focuses on securing AI for science by building dependable supercomputers. He is a National Science Foundation (NSF) Trusted Cyberinfrastructure (Trusted CI) Fellow, an affiliate of the Center for Artificial Intelligence Innovation, and a member of the Joint Laboratory for Extreme Scale Computing (JLESC).

He is leading an active research portfolio as the Principal Investigator of several NSF grants, e.g., Cybersecurity Innovation for Cyberinfrastructure (CICI: Security Data Lake), Research on Research Security (RoRS: Uncover HPC allocation abuses), and Formal Method in the Fields (FMiTF: Formalizing Federated Authentication); HPC-Quantum Computing observability (PQSee.com) is being commercialized through initial support of Campus Cyberinfrastructure (CC*: Post Quantum Cryptography Network Instrument). As a fellow of the NSF Cybersecurity Center of Excellence, he provides resiliency expertise to industry partners (IBM Research), mid-scale national testbeds (FABRIC), and DOE national labs.

Phuong Cao has been recognized with awards for his teaching and mentorship, including a IEEE Dependable Systems and Networks Best Paper Award (2014), Outstanding Mentor for CyberCorps®: Scholarship for Service and Fiddler Innovation Fellowship recipients (2025), and Art of HPC exhibit at Supercomputing 2024. Originally from Vietnam, he is currently a U.S. Permanent Resident (EB1).

Realizing resilient and secure supercomputing systems to advance open-science research, in the presence of accidental failures and cyber-attacks is his research goal. The key driver is cross-stack measurements of high-speed interconnects, AI application logs, and kernel probes from sustained petascale supercomputers (Blue Waters), HPC/GPU clusters (DeltaAI, Polaris), and exascale Aurora machine at the Argonne National Lab. These decade-long curated data (1PB) enables cyberattack detection, error propagation modeling across GPU architectures (Hopper/Blackwell/Rubin) and vendors, and understanding of quantum-resistant cryptography adoption, published in top conferences such as Supercomputing, USENIX Security, and IEEE Quantum Computing and Engineering. He is investigating reliability and security challenges of next-generation accelerators such as Quantum Processing Units (QPU) being integrated with HPC.